
`include "common_header.verilog"

//  *************************************************************************
//  File : top_enc8b10b.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2005 Morethanip
//  An der Steinernen Brueke 1, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Sebastien Marcellier
//  fbalay@morethanip.com
//  *************************************************************************
//  Decription : Encoder (Transmission code 8b/10b)
//  Version    : $Id: top_enc8b10b.v,v 1.3 2011/03/29 10:37:21 mr Exp $
//  *************************************************************************

module top_enc8b10b (

   din,
   kin,
   dout,
   clk,
`ifdef USE_CLK_ENA
   clk_ena,
`endif    
   rst);

input   [15:0] din;     //  Parallel byte of incoming data
input   [1:0] kin;      //  Special caracter request  	
output   [19:0] dout;   //  Parallel output data        
input   clk;            //  Main Clock 
`ifdef USE_CLK_ENA
input   clk_ena;        //  Enable clk
`endif
input   rst;            //  Asynchronous reset

wire    [19:0] dout; 

wire    disp_1;         //  Current Disparity
wire    disp_0;         //  Current Disparity
reg     disp_reg;       //  Registered Disparity

wire    vcc;
wire    gnd;

assign gnd = 1'b0;
assign vcc = 1'b1;

enc8b10b_xgxs U_ENC1 (

          .din(din[15:8]),
          .kin(kin[1]),
          .disp(disp_1),
          .rd_in(disp_0),
          .ce(vcc),
          .dout(dout[19:10]),
          .clk(clk),
        `ifdef USE_CLK_ENA
           .clk_ena(clk_ena),
        `endif           
          .sw_reset(gnd),
          .rst(rst));

enc8b10b_xgxs U_ENC0 (

          .din(din[7:0]),
          .kin(kin[0]),
          .disp(disp_0),
          .rd_in(disp_reg),
          .ce(vcc),
          .dout(dout[9:0]),
          .clk(clk),
        `ifdef USE_CLK_ENA
          .clk_ena(clk_ena),
        `endif            
          .sw_reset(gnd),
          .rst(rst));

always @(posedge rst or posedge clk)
   begin : process_1
   if (rst == 1'b 1)
      begin
      disp_reg <= 1'b 0;   
      end
   else
      begin
      
         `ifdef USE_CLK_ENA
            if(clk_ena == 1'b 1)
            begin
         `endif        
      
                disp_reg <= disp_1;   
      
         `ifdef USE_CLK_ENA
            end
         `endif
      
      end
   end

endmodule // module top_enc8b10b